The Small Computer System Interface (SCSI) is a parallel input/output bus often used to connect disk drives, CD-ROM's, tape drives and other peripheral devices to a computer bus. The SCSI bus is a bidirectional, multimaster bus which can accommodate peer to peer communications among multiple CPUs and multiple peripheral devices. Because of this versatility, the SCSI bus is becoming increasingly important in the microcomputer field. A SCSI host adapter is a device for connecting a SCSI bus to an expansion bus of a host computer.
The apparatus of the present invention provides a means for enhancing performance of a SCSI host adapter, by reducing access time for the computer bus. The present invention can be used with any peripheral bus providing similar performances as those derived when used with a SCSI bus.
The present invention generally comprises a complete multifunctional SCSI chip that is shown to be in communication with a host bus. The host bus can be either the Industry Standard Architecture (ISA), the Micro Channel Architecture (MCA), the Extended Industry Standard Architecture (EISA), or other bus architecture as taught by U.S. patent application Ser. No. 667,754 filed on Mar. 11, 1991 by the inventor of the present invention, which application is hereby incorporated by reference.
More particularly, the apparatus generally comprises an internal data bus with a main FIFO ("first-in, first-out") buffer coupled to it. A first interface means is provided for coupling the SCSI bus to the internal data bus and a second interface means is provided for coupling the host computer bus to the internal data bus. Control logic gating means are provided for causing data communicated between the SCSI bus and the first interface means to flow onto the internal data bus and to further flow from the internal data bus into the main FIFO buffer (or in the opposite direction, as required).
The second interface means is used by the host computer when writing data to or reading data from the main FIFO. In the first case the host writes the data to a prestore register, which is located between the host bus and main FIFO. The prestore register does not require the host to wait for the next available internal data bus cycle, but instead buffers the data until an appropriate cycle is available. When this occurs, the prestore register moves its data to the main FIFO. This ensures the prestore register will be ready (i.e., empty) when the next host write cycle occurs. When data is being read from the main FIFO, the host accesses a prefetch register which lies between the host and the main FIFO. Data in this register is fetched from the main FIFO during available internal data bus cycles. This allows the data to be available when the host requests it, eliminating host waiting for an internal data bus cycle. By thus eliminating wait states, overall system performance is significantly enhanced.
The apparatus of the present invention is well suited for single chip implementation of an SCSI host adapter. Dual small first in, first out (FIFO) buffers in the first interface means are used to provide a circuit which supports both asynchronous and synchronous SCSI bus transfer modes. The prefetch register as well as the prestore register are implemented to reduce delays in the form of additional wait states. In its presently preferred embodiment, the only external components needed are a suitable oscillator.
It should be appreciated that the smaller FIFOs are high-speed, low latency devices which support the offset between data requests and acknowledges (required for synchronous SCSI), while the larger main FIFO is a slower device intended to compensate for the difference between data rates of the host and SCSI buses.
The host adapter of the present invention supports asynchronous and synchronous protocols conforming to the SCSI specification known as the SCSI-2 specification proposed by the American National Standards Institute (ANSI) and further described in the X3.131-199x; X3 Project 503-D prepared by the Technical Committee X3T9 of the I/O interface accredited Standards Committee, X3-Information Processing Systems. These documents are also hereby incorporated by reference.
The apparatus of the present invention further includes logic circuitry for handling SCSI bus arbitration, logic for automatic control of request/acknowledge handshakes and interrupt generation logic. The apparatus provides FIFO buffering of data as described above with additional buffering provided by the prestore and prefetch registers.
The apparatus of the present invention is thus very flexible and well adapted for use in a wide variety of SCSI applications and is particularly well adapted for, but not limited to, use in SCSI applications.
For a more complete understanding of the preferred embodiment of the present invention and its many objects and advantages, reference may be had to the following detailed specification and to the accompanying drawings.